The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 10, 2016
Filed:
Nov. 04, 2014
Applicant:
Hrl Laboratories Llc, Malibu, CA (US);
Inventors:
Florian G. Herrault, Agoura Hills, CA (US);
Alexandros Margomenos, Pasadena, CA (US);
Miroslav Micovic, Los Angeles, CA (US);
Melanie S. Yajima, Los Angeles, CA (US);
Eric M. Prophet, Santa Barbara, CA (US);
Assignee:
HRL Laboratories, LLC, Malibu, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 23/373 (2006.01); H01L 23/40 (2006.01); H01L 21/48 (2006.01); H01L 23/00 (2006.01); H01L 21/027 (2006.01); H01L 21/3213 (2006.01); H01L 21/3205 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 23/3736 (2013.01); H01L 21/0274 (2013.01); H01L 21/32051 (2013.01); H01L 21/32135 (2013.01); H01L 21/4882 (2013.01); H01L 21/768 (2013.01); H01L 21/76841 (2013.01); H01L 23/3732 (2013.01); H01L 23/40 (2013.01); H01L 24/83 (2013.01); H01L 2224/8385 (2013.01); H01L 2224/83203 (2013.01); H01L 2924/01022 (2013.01); H01L 2924/01028 (2013.01); H01L 2924/01029 (2013.01); H01L 2924/01079 (2013.01); H01L 2924/0665 (2013.01); H01L 2924/1033 (2013.01); H01L 2924/10253 (2013.01); H01L 2924/10272 (2013.01); H01L 2924/10329 (2013.01); H01L 2924/10335 (2013.01); H01L 2924/14 (2013.01); H01L 2924/2064 (2013.01); H01L 2924/20101 (2013.01); H01L 2924/20102 (2013.01); H01L 2924/20103 (2013.01); H01L 2924/20105 (2013.01);
Abstract
A method for forming a wafer level heat spreader includes providing a mesh wafer, the mesh wafer having a plurality of openings and mesh regions between the openings, bonding the mesh wafer to a backside of an integrated circuit (IC) wafer, the IC wafer comprising a plurality of circuits; and electroplating a heat sink material through the plurality of openings and onto to the backside of the IC wafer.