The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 10, 2016
Filed:
Dec. 29, 2011
Applicants:
Yun-hyuck Ji, Gyeonggi-do, KR;
Beom-yong Kim, Gyeonggi-do, KR;
Seung-mi Lee, Gyeonggi-do, KR;
Inventors:
Assignee:
SK Hynix Inc., Gyeonggi-do, KR;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/49 (2006.01); H01L 21/8238 (2006.01); H01L 21/28 (2006.01); H01L 21/02 (2006.01); H01L 29/51 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823807 (2013.01); H01L 21/02148 (2013.01); H01L 21/02274 (2013.01); H01L 21/28202 (2013.01); H01L 21/823828 (2013.01); H01L 21/823842 (2013.01); H01L 29/495 (2013.01); H01L 29/4966 (2013.01); H01L 29/518 (2013.01);
Abstract
A semiconductor device includes a gate dielectric layer over a substrate, a metal layer over the gate dielectric layer, a capping layer over the metal layer, wherein the capping layer includes a plurality of dipole forming elements concentrated at the interface between the metal layer and the capping layer.
Ji, Yun-Hyuck. (2016). Semiconductor device with metal gate and high-k dielectric layer, cmos integrated circuit, and method for fabricating the same (U.S. Patent No. 9337108). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9337108
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile