The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 10, 2016
Filed:
May. 23, 2013
Applicant:
SK Hynix Memory Solutions Inc., San Jose, CA (US);
Inventors:
Arunkumar Subramanian, San Jose, CA (US);
Frederick K. H. Lee, Mountain View, CA (US);
Xiangyu Tang, San Jose, CA (US);
Lingqi Zeng, Turlock, CA (US);
Jason Bellorado, San Jose, CA (US);
Assignee:
SK Hynix Memory Solutions Inc., San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/04 (2006.01); G11C 16/06 (2006.01); G11C 16/10 (2006.01); G11C 16/26 (2006.01);
U.S. Cl.
CPC ...
G11C 16/10 (2013.01); G11C 16/26 (2013.01);
Abstract
A charge constrained bit sequence is processed to obtain a lower bound on a number of bit errors associated with the charge constrained bit sequence. The lower bound is compared against an error correction capability threshold associated with an error correction decoder. In the event the lower bound is greater than or equal to the error correction decoder threshold, an error correction decoding failure is predicted.