The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 10, 2016

Filed:

Mar. 02, 2015
Applicant:

Kabushiki Kaisha Toshiba, Minato-ku, JP;

Inventors:

Takeshi Takagi, Yokkaichi, JP;

Masaki Yamato, Yokkaichi, JP;

Hiroyuki Ode, Yokkaichi, JP;

Takeshi Yamaguchi, Yokkaichi, JP;

Toshiharu Tanaka, Yokkaichi, JP;

Assignee:

KABUSHIKI KAISHA TOSHIBA, Minato-ku, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 13/00 (2006.01); G06F 11/07 (2006.01);
U.S. Cl.
CPC ...
G11C 13/0069 (2013.01); G06F 11/073 (2013.01); G06F 11/076 (2013.01); G06F 11/0793 (2013.01); G11C 13/0064 (2013.01); G11C 13/0097 (2013.01);
Abstract

A nonvolatile memory device comprises a memory cell comprising a variable resistance element connected between a couple of wirings and a control circuit applying a voltage between the couple of wirings connected to the memory cell. In data rewriting, the control circuit repeats a first voltage application step of applying a first write voltage between the couple of wirings and a first verify step of applying a first voltage lower than the first write voltage between the couple of wirings and comparing a cell current through the cell with a first threshold current, the steps repeated until a magnitude relation of the cell current and the first threshold current satisfies a first condition. If the first condition is satisfied, the circuit performs a second voltage application step of applying a second write voltage between the couple of wirings.


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