The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 10, 2016

Filed:

Aug. 24, 2012
Applicants:

Susan J. Eggers, Seattle, WA (US);

Luis Ceze, Seattle, WA (US);

Emily Fortuna, Seattle, WA (US);

Owen Anderson, San Jose, CA (US);

Inventors:

Susan J. Eggers, Seattle, WA (US);

Luis Ceze, Seattle, WA (US);

Emily Fortuna, Seattle, WA (US);

Owen Anderson, San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/00 (2006.01); G06F 11/36 (2006.01); G06F 11/07 (2006.01); G06F 9/45 (2006.01);
U.S. Cl.
CPC ...
G06F 11/3668 (2013.01); G06F 8/437 (2013.01); G06F 11/0712 (2013.01); G06F 11/0772 (2013.01);
Abstract

Devices and methods of providing hardware support for dynamic type checking are provided. In some embodiments, a processor includes a type check register and support for one or more checked load instructions. In some embodiments, normal load instructions are replaced by a compiler with the checked load instructions. In some embodiments, to perform a checked load, an error handler instruction location is stored in the type check register, and a type tag operand is compared to a type tag stored in the loaded memory location. If the comparison succeeds, execution may proceed normally. If the comparison fails, execution may be transferred to the error handler instruction. In some embodiments, type prediction is performed to determine whether a checked load instruction is likely to fail.


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