The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 10, 2016

Filed:

Apr. 17, 2014
Applicant:

Cisco Technology, Inc., San Jose, CA (US);

Inventors:

Scott Phuong, Sunnyvale, CA (US);

Tao Wang, Cupertino, CA (US);

Kumar Sidhartha, Bangalore, IN;

Assignee:

Cisco Technology, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/32 (2006.01); G06F 11/22 (2006.01);
U.S. Cl.
CPC ...
G06F 11/2284 (2013.01); G06F 1/324 (2013.01); G06F 1/3293 (2013.01);
Abstract

Presented herein are methods for budgeting power during a power-on self-test (POST) sequence. A determination is made for one or more stages of a power-on-self-test sequence of a system, whether a power profile of a particular stage is greater than a power budget for that stage. The power profile specifies a maximum power consumption as determined by the characteristics of the system and the power budget specifies a power consumption currently allocated to the system. When the power profile is greater than the power budget for that stage, power consumption of the system during the power-on-self-test sequence is limited such that the system does not consume more power than specified by the power budget.


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