The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 10, 2016

Filed:

Aug. 14, 2013
Applicant:

Nvidia Corporation, Santa Clara, CA (US);

Inventors:

Ziyad S. Hakura, Gilroy, CA (US);

Pierre Souillot, Berkeley, CA (US);

Cynthia Allison, Madison, AL (US);

Dale L. Kirkland, Madison, AL (US);

Assignee:

NVIDIA Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06T 1/60 (2006.01); G06F 9/38 (2006.01); G06T 15/00 (2011.01); G06T 15/40 (2011.01); G06T 1/20 (2006.01); G09G 5/395 (2006.01); G09G 5/00 (2006.01); G06T 15/50 (2011.01); G06F 12/08 (2016.01); G06F 9/44 (2006.01); G06T 15/80 (2011.01);
U.S. Cl.
CPC ...
G06F 9/38 (2013.01); G06F 9/44 (2013.01); G06F 12/0808 (2013.01); G06F 12/0875 (2013.01); G06T 1/20 (2013.01); G06T 1/60 (2013.01); G06T 15/005 (2013.01); G06T 15/405 (2013.01); G06T 15/503 (2013.01); G06T 15/80 (2013.01); G09G 5/003 (2013.01); G09G 5/395 (2013.01); G06F 2212/302 (2013.01); Y02B 60/1225 (2013.01);
Abstract

One embodiment of the present invention includes a method for performing a multi-pass tiling test. The method includes combining a plurality of bounding boxes to generate a coarse bounding box. The method further includes identifying a first cache tile associated with a render surface and determining that the coarse bounding box intersects the first cache tile. The method further includes comparing each bounding box included in the plurality of bounding boxes against the first cache tile to determine that a first set of one or more bounding boxes included in the plurality of bounding boxes intersects the first cache tile. Finally, the method includes, for each bounding box included in the first set of one or more bounding boxes, processing one or more graphics primitives associated with the bounding box. One advantage of the disclosed technique is that the number of intersection calculations performed for each cache tile is reduced.


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