The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 10, 2016

Filed:

Sep. 07, 2010
Applicants:

Marduke Yousefpor, San Jose, CA (US);

Steven Porter Hotelling, Los Gatos, CA (US);

Kevin J. White, Los Gatos, CA (US);

Inventors:

Marduke Yousefpor, San Jose, CA (US);

Steven Porter Hotelling, Los Gatos, CA (US);

Kevin J. White, Los Gatos, CA (US);

Assignee:

Apple Inc., Cupertino, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 3/041 (2006.01); G06F 3/045 (2006.01); G06F 3/044 (2006.01); G02F 1/1333 (2006.01); G02F 1/1362 (2006.01);
U.S. Cl.
CPC ...
G06F 3/044 (2013.01); G02F 1/1362 (2013.01); G02F 1/13338 (2013.01); G06F 3/0412 (2013.01); G06F 3/0418 (2013.01); H01L 2224/48091 (2013.01);
Abstract

Clamping of a circuit element of a touch screen, such as a gate line of the display system of the touch screen, to a fixed voltage is provided. The circuit element can be clamped during a touch phase and unclamped during a display phase of the touch screen. A gate line system of a touch screen can include a first transistor with a source or drain connected to a first gate line, a second transistor with a source or drain connected to a second gate line, and a common conductive pathway connecting gates of the first and second transistors. A synchronization system can switch the first and second transistors to connect the first and second gate lines to a fixed voltage during a touch phase, and can switch the first and second transistors to disconnect the first and second gate lines from the fixed voltage during a display phase.


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