The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 10, 2016

Filed:

Oct. 11, 2013
Applicant:

Memsensing Microsystems (Suzhou, China) Co., Ltd., Suzhou, Jiangsu Province, CN;

Inventors:

Gang Li, Suzhou, CN;

Wei Hu, Suzhou, CN;

Jia-Xin Mei, Suzhou, CN;

Rui-Fen Zhuang, Suzhou, CN;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/84 (2006.01); H01L 23/538 (2006.01); H01L 25/065 (2006.01); B81C 1/00 (2006.01);
U.S. Cl.
CPC ...
B81C 1/00238 (2013.01); B81C 2203/0792 (2013.01);
Abstract

The invention relates to an integrated chip with an MEMS and an integrated circuit mounted therein and a method for manufacturing the same. The method includes the steps of: S: providing a first chip, wherein the first chip comprises a first substrate, an MEMS component layer formed on the first substrate and comprising a first electrical bonding point disposed on MEMS the component layer; S: providing a second chip with an IC integrated circuit, wherein the second chip comprises a second lead layer and a second electrical bonding point; S: bonding the first electrical bonding point and the second electrical bonding point; S: processing a thinning operation for the bottom surface of the first substrate; and S: forming an electrical connection layer electrically connected to an external circuit on the bottom surface of the first substrate.


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