The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 03, 2016

Filed:

Jun. 14, 2012
Applicants:

San Jeow Cheng, Singapore, SG;

Yuan Gao, Singapore, SG;

Yuanjin Zheng, Singapore, SG;

Chun Huat Heng, Singapore, SG;

Inventors:

San Jeow Cheng, Singapore, SG;

Yuan Gao, Singapore, SG;

Yuanjin Zheng, Singapore, SG;

Chun Huat Heng, Singapore, SG;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04B 7/02 (2006.01); H04L 1/02 (2006.01); H04L 27/12 (2006.01); H04L 27/156 (2006.01);
U.S. Cl.
CPC ...
H04L 27/12 (2013.01); H04L 27/156 (2013.01);
Abstract

According to embodiments of the present invention, a frequency shift keying transmitter is provided. The frequency shift keying transmitter includes a logic gate arrangement that produces an output signal having a frequency that depends on input signals to the logic gate arrangement, a clock generator coupled to the logic gate arrangement, the clock generator adapted to produce a clock signal, and a sampling arrangement coupled to the logic gate arrangement, the sampling arrangement adapted to receive a data signal, wherein the sampling arrangement is configured to sample the clock signal to generate periodic waveforms delayed from each other by an interval determined by the point the clock signal is sampled, wherein the sampling arrangement is configured to be controlled by the data signal to have the logic gate arrangement select periodic waveforms that are delayed from each other by one of a set of intervals associated with the data signal, to be used as the input signals to the logic gate arrangement to produce the output signal.


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