The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 03, 2016

Filed:

Jul. 08, 2015
Applicants:

Ncku Research and Development Foundation, Tainan, TW;

Himax Technologies Limited, Tainan, TW;

Inventors:

Soon-Jyh Chang, Tainan, TW;

Yu-Po Cheng, Tainan, TW;

Yen-Long Lee, Tainan, TW;

Chung-Ming Huang, Tainan, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/08 (2006.01); H03L 7/093 (2006.01); H04L 1/20 (2006.01); H04L 7/00 (2006.01); H04B 1/16 (2006.01); H04B 1/04 (2006.01);
U.S. Cl.
CPC ...
H04L 1/205 (2013.01); H04B 1/16 (2013.01); H04L 7/0016 (2013.01); H04L 7/0054 (2013.01); H04B 2001/0416 (2013.01);
Abstract

A clock and data recovery circuit and a method for estimating jitter tolerance thereof are provided. A first phase signal is generated by a phase detector, and a second phase signal is used to generate a clock signal. The second phase signal is set to be identical to the first phase signal during an operation mode. A counting is started and the first phase signal is inversed to generate the second phase signal during a test mode. Whether a data signal has an error is determined. The counting is stopped to generate a count value when determining that the data signal has the error during the test mode. A tracing speed is computed according to the count value and a predetermined unit interval.


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