The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 03, 2016

Filed:

Jul. 10, 2014
Applicant:

SK Hynix Inc., Gyeonggi-do, KR;

Inventors:

Sung Cheoul Kim, Gyeonggi-do, KR;

Kang Sik Choi, Gyeonggi-do, KR;

Assignee:

SK Hynix Inc., Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/02 (2006.01); H01L 29/76 (2006.01); H01L 29/788 (2006.01); H01L 21/8239 (2006.01); H01L 45/00 (2006.01); H01L 27/24 (2006.01);
U.S. Cl.
CPC ...
H01L 45/1233 (2013.01); H01L 27/2436 (2013.01); H01L 27/2463 (2013.01); H01L 45/04 (2013.01); H01L 45/126 (2013.01);
Abstract

A memory cell array includes a semiconductor substrate, a first word line formed on the semiconductor substrate, a second word line formed on the semiconductor substrate and extending substantially parallel to the first word line, a first inter-pattern insulating layer interposed between the first and second word lines, first active pillars formed within the first word line and arranged along the first word line at a first interval, and second active pillars formed within the second word lines, and arranged along the second word line to face the first active pillars, respectively, with the first inter-pattern insulating layer interposed therebetween.


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