The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 03, 2016

Filed:

Dec. 18, 2013
Applicants:

Korea Institute of Science and Technology, Seoul, KR;

The United States of America, As Represented BY the Secretary of the Navy, Arlington, VA (US);

Inventors:

Joon Yeon Chang, Seoul, KR;

Jin Ki Hong, Seoul, KR;

Jin Dong Song, Seoul, KR;

Mark Johnson, Potomac, MD (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/173 (2006.01); H01L 43/02 (2006.01); H01L 27/22 (2006.01); H03K 19/0175 (2006.01); H03K 19/16 (2006.01); H01L 43/08 (2006.01); G11C 11/16 (2006.01);
U.S. Cl.
CPC ...
H01L 43/02 (2013.01); G11C 11/161 (2013.01); H01L 27/22 (2013.01); H01L 43/08 (2013.01); H03K 19/017581 (2013.01); H03K 19/16 (2013.01);
Abstract

A non-volatile reconfigurable logic device executing logical operations and a memory function and controlled by a magnetic field is provided. The reconfigurable logic device includes i) at least one semiconductor device; and ii) a pair of magnetic field controlled devices respectively spaced apart from both sides of the semiconductor device and that are adapted to generate magnetic field leakage to control the semiconductor device. The semiconductor device includes i) a first semiconductor layer; and ii) a second semiconductor layer located on the first semiconductor layer. One of the first semiconductor layer and the second semiconductor layer is a p-type semiconductor layer and the other is an n-type semiconductor layer.


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