The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 03, 2016

Filed:

Apr. 27, 2011
Applicants:

Andrew Gabriel Rinzler, St. Newberry, FL (US);

Pooja Wadhwa, Chandler, AZ (US);

Jing Guo, Gainesville, FL (US);

Gyungseon Seol, Gainesville, FL (US);

Inventors:

Andrew Gabriel Rinzler, St. Newberry, FL (US);

Pooja Wadhwa, Chandler, AZ (US);

Jing Guo, Gainesville, FL (US);

Gyungseon Seol, Gainesville, FL (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 31/0224 (2006.01); H01L 31/07 (2012.01);
U.S. Cl.
CPC ...
H01L 31/022433 (2013.01); H01L 31/07 (2013.01); Y02E 10/50 (2013.01);
Abstract

Various systems and methods are provided for Schottky junction solar cells. In one embodiment, a solar cell includes a mesh layer formed on a semiconductor layer and an ionic layer formed on the mesh layer. The ionic layer seeps through the mesh layer and directly contacts the semiconductor layer. In another embodiment, a solar cell includes a first mesh layer formed on a semiconductor layer, a first metallization layer coupled to the first mesh layer, a second high surface area electrically conducting electrode coupled to the first metallization layer by a gate voltage, and an ionic layer in electrical communication with the first mesh layer and the second high surface area electrically conducting electrode. In another embodiment, a solar cell includes a grid layer formed on a semiconductor layer and an ionic layer in electrical communication with the grid layer and the semiconductor layer.


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