The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 03, 2016

Filed:

Mar. 27, 2012
Applicants:

Deepa Ratakonda, San Jose, CA (US);

Peter Smeys, San Jose, CA (US);

Shuxian Chen, Fremont, CA (US);

Girish Venkitachalam, San Jose, CA (US);

Inventors:

Deepa Ratakonda, San Jose, CA (US);

Peter Smeys, San Jose, CA (US);

Shuxian Chen, Fremont, CA (US);

Girish Venkitachalam, San Jose, CA (US);

Assignee:

Altera Corporation, San Jose, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/06 (2006.01); H01L 49/02 (2006.01); H01L 27/108 (2006.01);
U.S. Cl.
CPC ...
H01L 28/60 (2013.01); H01L 27/10855 (2013.01);
Abstract

An integrated circuit may include interconnects formed from alternating metal interconnect layers and inter-metal dielectric layers. A metal-insulator-metal capacitor may be formed within a selected inter-metal dielectric layer. The metal-insulator-metal capacitor may include first and second capacitor electrodes. The first capacitor electrode may contact a first conductive interconnect line in an underlying metal interconnect layer. The second capacitor electrode may overlap the first capacitor electrode and a portion of a second conductive interconnect line in the underlying metal layer. A via may be formed between the underlying metal interconnect layer and an additional metal interconnect layer. The via may simultaneously contact the second capacitor electrode and the second conductive interconnect line.


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