The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 03, 2016

Filed:

Jul. 14, 2009
Applicants:

Wibo D. Van Noort, Westbrook, ME (US);

Theodore J. Letavic, Putnam Valley, NY (US);

Francis Zaato, Fishkill, NY (US);

Inventors:

Wibo D. Van Noort, Westbrook, ME (US);

Theodore J. Letavic, Putnam Valley, NY (US);

Francis Zaato, Fishkill, NY (US);

Assignee:

NXP B.V., Eindhoven, NL;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/02 (2006.01); H01L 27/115 (2006.01); G11C 16/04 (2006.01); G11C 27/00 (2006.01); H01L 27/102 (2006.01); H01L 27/105 (2006.01); H01L 29/792 (2006.01); H03K 5/13 (2014.01); H03M 1/80 (2006.01); H01L 21/8249 (2006.01); H03K 5/00 (2006.01);
U.S. Cl.
CPC ...
H01L 27/115 (2013.01); G11C 16/0416 (2013.01); G11C 27/005 (2013.01); H01L 27/105 (2013.01); H01L 27/1026 (2013.01); H01L 27/11517 (2013.01); H01L 29/792 (2013.01); H03K 5/133 (2013.01); H03M 1/802 (2013.01); G11C 2216/10 (2013.01); H01L 21/8249 (2013.01); H03K 2005/00019 (2013.01);
Abstract

An integrated circuit is provided, which comprises at least one first group each having at least one analog unit; and at least one second group each having at least one electronically settable semi-permanent switching unit coupled to the at least analog unit of the first group for trimming the first group and having at least one many-times-programmable and non-volatile cell (MTP). Each many-times-programmable cell (MTP) comprises at least one MOS transistor having a floating gate (FG) with a tunnel oxide (TO) and a first capacitor coupled to the floating gate (FG). The capacitance of the first capacitor is substantially larger than a gate-channel capacitance of the MOS transistor.


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