The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 03, 2016

Filed:

Dec. 06, 2013
Applicant:

Altera Corporation, San Jose, CA (US);

Inventors:

Christopher F. Lane, San Jose, CA (US);

Arifur Rahman, San Jose, CA (US);

Assignee:

Altera Corporation, San Jose, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/52 (2006.01); H01L 27/02 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0207 (2013.01); H01L 21/76801 (2013.01);
Abstract

Integrated circuits with backside power delivery capabilities are provided. An integrated circuit may include a substrate having front and back surfaces, a first interconnect stack formed on the front surface, and a second interconnect stack formed on the back surface. Routing structures that carry data signals, control signals, and other user signals may be formed only in the first interconnect stack. A large majority of routing structures that carry power supply signals may be formed in the second interconnect stack. Decoupling capacitor circuitry such as deep trench capacitors may be formed in the back surface of the substrate. The integrated circuit may be mounted on a package substrate. The first interconnect stack may be coupled to the package substrate via wire bond pads, whereas the second interconnect stack may be coupled to the package substrate via an array of solder bumps.


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