The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 03, 2016

Filed:

Jun. 01, 2015
Applicant:

The Board of Trustees of the University of Illinois, Urbana, IL (US);

Inventors:

J. Gary Eden, Champaign, IL (US);

Paul A. Tchertchian, Mission Viejo, CA (US);

Clark J. Wagner, Rowland Heights, CA (US);

Dane J. Sievers, Fisher, IL (US);

Thomas J. Houlahan, Urbana, IL (US);

Benben Li, Urbana, IL (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01J 17/36 (2006.01); H01L 29/73 (2006.01); H01J 17/06 (2006.01); H01J 17/49 (2012.01); H01L 33/02 (2010.01);
U.S. Cl.
CPC ...
H01J 17/36 (2013.01); H01J 17/066 (2013.01); H01J 17/49 (2013.01); H01J 17/497 (2013.01); H01L 29/66234 (2013.01); H01L 29/73 (2013.01); H01L 33/02 (2013.01);
Abstract

Logic devices are provided in multiple sub-collector and sub-emitter microplasma devices formed in thin and flexible, or inflexible, semiconductor materials. Logic operations are provided with one of a plurality of microplasmas forming sub-collectors with a common emitter, or a common collector plasma with a plurality of sub-emitter regions in a solid state semi-conductor pn-junction, and generating a logic output from an electrode, based upon electrode inputs to two other electrodes.


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