The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 03, 2016

Filed:

Dec. 16, 2011
Applicants:

Shinji Yonezawa, Tokyo, JP;

Hirokuni Yano, Tokyo, JP;

Toshikatsu Hida, Kanagawa, JP;

Tatsuya Sumiyoshi, Kanagawa, JP;

Inventors:

Shinji Yonezawa, Tokyo, JP;

Hirokuni Yano, Tokyo, JP;

Toshikatsu Hida, Kanagawa, JP;

Tatsuya Sumiyoshi, Kanagawa, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 13/00 (2006.01); G06F 13/28 (2006.01); G11C 11/56 (2006.01); G06F 12/02 (2006.01); G11C 16/04 (2006.01);
U.S. Cl.
CPC ...
G11C 11/5628 (2013.01); G06F 12/0246 (2013.01); G06F 2212/7201 (2013.01); G06F 2212/7207 (2013.01); G11C 16/0483 (2013.01);
Abstract

A memory system of one embodiment includes: a nonvolatile memory including a plurality of word lines each connected to memory cells, each one of the memory cells being capable storing two bits, the memory cells connected to one of the plurality of word lines constituting an upper page and a lower page, each one of the pages being a unit of data programming; a random access memory configured to store an address translation table indicating relationships between logical addresses designated by a host and physical addresses in the nonvolatile memory. The memory system of the embodiment further includes a memory controller which execute data fixing for saving the address translation table from the random access memory to the nonvolatile memory; and write dummy data to at least one page subsequent to the page in which valid data has been written in the nonvolatile memory before executing the data fixing.


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