The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 03, 2016

Filed:

Oct. 21, 2014
Applicant:

Xilinx, Inc., San Jose, CA (US);

Inventors:

Dhruv Choksey, San Jose, CA (US);

Terence J. Magee, San Francisco, CA (US);

Assignee:

XILINX, INC., San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 11/4063 (2006.01);
U.S. Cl.
CPC ...
G11C 11/4063 (2013.01);
Abstract

In an example, a memory control device includes an output circuit, an output delay unit, and a write-levelization controller. The output circuit is coupled to provide an output signal comprising a data signal or data strobe signal for a synchronous dynamic random access memory (SDRAM) system having a plurality of ranks. The output delay unit is coupled to apply an output delay to a bitstream to be transmitted to generate the output signal. The output delay includes an aggregate of a de-skew delay and a write-levelization delay. The write-levelization delay controller is coupled to adjust the write-levelization delay for each write transaction to the SDRAM system of a plurality of write transactions based on a selected rank of the plurality of ranks. The de-skew delay is the same across the plurality of ranks for each of the plurality of write transactions.


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