The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 03, 2016

Filed:

Apr. 03, 2015
Applicants:

Chan-kyung Kim, Hwaseong-si, KR;

Kee-won Kwon, Seongnam-si, KR;

Su-a Kim, Seongnam-si, KR;

Chul-woo Park, Yongin-si, KR;

Jae-youn Youn, Seoul, KR;

Inventors:

Chan-Kyung Kim, Hwaseong-si, KR;

Kee-Won Kwon, Seongnam-si, KR;

Su-A Kim, Seongnam-si, KR;

Chul-Woo Park, Yongin-si, KR;

Jae-Youn Youn, Seoul, KR;

Assignee:

SAMSUNG ELECTRONICS CO., LTD., Samsung-ro, Yeongtong-gu, Suwon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01); G11C 11/16 (2006.01); G11C 5/08 (2006.01); G11C 7/06 (2006.01); G11C 5/02 (2006.01); G11C 13/00 (2006.01); G11C 11/4091 (2006.01);
U.S. Cl.
CPC ...
G11C 11/16 (2013.01); G11C 5/025 (2013.01); G11C 5/08 (2013.01); G11C 7/065 (2013.01); G11C 11/1653 (2013.01); G11C 11/1673 (2013.01); G11C 13/004 (2013.01); G11C 13/0023 (2013.01); G11C 11/4091 (2013.01); G11C 2013/0042 (2013.01); G11C 2213/79 (2013.01); G11C 2213/82 (2013.01);
Abstract

A memory core of a resistive type memory device includes at least a first resistive type memory cell coupled to a bit-line, a first resistance to voltage converter and a bit-line sense amplifier. The first resistance to voltage converter is coupled to the bit-line at a first node. The first resistance to voltage converter converts a resistance of the first resistive type memory cell to a corresponding voltage based on a read column selection signal. The bit-line sense amplifier is coupled to the bit-line at the first node and is coupled to a complementary bit-line at a second node. The bit-line sense amplifier senses and amplifies a voltage difference of the bit-line and the complementary bit-line in response to a sensing control signal.


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