The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 03, 2016

Filed:

Feb. 24, 2014
Applicant:

Ambarella, Inc., Santa Clara, CA (US);

Inventor:

Manish K. Singh, Mountain House, CA (US);

Assignee:

Ambarella, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06K 9/36 (2006.01); G06K 9/32 (2006.01); G06T 11/00 (2006.01); G06T 3/40 (2006.01); G06T 5/00 (2006.01); G06K 9/62 (2006.01); G06T 3/00 (2006.01);
U.S. Cl.
CPC ...
G06T 5/00 (2013.01); G06K 9/6206 (2013.01); G06T 3/0093 (2013.01);
Abstract

An apparatus generally having a first memory, a second memory and a circuit is disclosed. The first memory may be configured to store a warp table. The warp table is generally accessed through a single data port of the first memory. The second memory may be configured to buffer an input image. The input image may have a plurality of input pixels arranged in two dimensions. The circuit may be configured to generate an output image by a warp correction of an input image. The warp correction may be defined by the warp table. The output image may include a plurality of output pixels. At least one of the output pixels may be generated during each clock cycle of the circuit.


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