The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 03, 2016
Filed:
Aug. 25, 2014
Applicant:
Xilinx, Inc., San Jose, CA (US);
Inventors:
Mehrdad E. Dehkordi, San Jose, CA (US);
Marvin Tom, Cupertino, CA (US);
Sridhar Krishnamurthy, San Jose, CA (US);
Abhishek Joshi, Fremont, CA (US);
Assignee:
XILINX, INC., San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); G06F 1/10 (2006.01);
U.S. Cl.
CPC ...
G06F 17/5072 (2013.01); G06F 17/5077 (2013.01); G06F 1/10 (2013.01); G06F 17/5027 (2013.01); G06F 2217/62 (2013.01);
Abstract
Clock region partitioning and clock routing includes creating partitions for a plurality of clocks of a circuit design, and legalizing the partitions using a processor according to a number of clocks in each partition and assignment of clock distribution tracks. Roots for implementing clock trees of the clocks are selected within the partitions.