Cache memory error detection circuits for detecting bit flips in valid indicators in cache memory following invalidate operations, and related methods and processor-based systems

Abstract

Aspects disclosed herein include cache memory error detection circuits for detecting bit flips in valid indicators (e.g., valid bits) in cache memory following invalidate operations. Related methods and processor-based systems are also disclosed. If a cache hit results from access to a cache entry following an invalidate operation, a bit flip(s) has occurred in a valid indicator of the cache entry. This is because the valid indicator should indicate an invalid state following the invalidate operation of the cache entry, as opposed to a valid state. Thus, a cache memory error detection circuit is configured to determine if an invalidate operation was performed on the cache entry. The cache memory error detection circuit can cause a cache miss or an error for the accessed cache entry to be generated as a result, even though the valid indicator for the cache entry indicates a valid state due to the bit flip(s).