The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 03, 2016
Filed:
Mar. 13, 2012
Jin-han Kim, Daegu, KR;
Yeong-seop Lee, Gumi-si, KR;
Seok-hong Jeong, Suwon-si, KR;
Myung-sop Lee, Gumi-si, KR;
Kyoung-suk OH, Gumi-si, KR;
Jung-hun Woo, Gumi-si, KR;
Dong-chul Lee, Gumi-si, KR;
Jong-hyun Yim, Daegu, KR;
Sung-il Jang, Chilgok-gun, KR;
Yong-gu Cho, Uiwang-si, KR;
Hyoung-jun Go, Gumi-si, KR;
Kyoung-hun Kim, Gumi-si, KR;
Jeong-eun Kim, Gumi-si, KR;
Hyeon-beom Kim, Gumi-si, KR;
Dae-bin Noh, Gumi-si, KR;
Jae-young Park, Daegu, KR;
Eun-jin Baek, Gumi-si, KR;
Chung-hee Lee, Gumi-si, KR;
Sung-ho Jung, Gumi-si, KR;
Jae-wook Cho, Gumi-si, KR;
Jin-Han Kim, Daegu, KR;
Yeong-Seop Lee, Gumi-si, KR;
Seok-Hong Jeong, Suwon-si, KR;
Myung-Sop Lee, Gumi-si, KR;
Kyoung-Suk Oh, Gumi-si, KR;
Jung-Hun Woo, Gumi-si, KR;
Dong-Chul Lee, Gumi-si, KR;
Jong-Hyun Yim, Daegu, KR;
Sung-Il Jang, Chilgok-gun, KR;
Yong-Gu Cho, Uiwang-si, KR;
Hyoung-Jun Go, Gumi-si, KR;
Kyoung-Hun Kim, Gumi-si, KR;
Jeong-Eun Kim, Gumi-si, KR;
Hyeon-Beom Kim, Gumi-si, KR;
Dae-Bin Noh, Gumi-si, KR;
Jae-Young Park, Daegu, KR;
Eun-Jin Baek, Gumi-si, KR;
Chung-Hee Lee, Gumi-si, KR;
Sung-Ho Jung, Gumi-si, KR;
Jae-Wook Cho, Gumi-si, KR;
Samsung Electronics Co., Ltd., Suwon-si, KR;
Abstract
Provided herein is a capacitive-type touch panel. The capacitive-type touch panel may include a first transparent substrate, a first conductive layer positioned on the first transparent substrate, a sensor layer having a second conductive layer spaced from the first conductive layer by a spacer, and a second transparent substrate positioned on the sensor layer. The first conductive layer and the second conductive layer may be transparent.