The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 03, 2016

Filed:

Mar. 14, 2014
Applicant:

Altera Corporation, San Jose, CA (US);

Inventors:

Zahir Parpia, Toronto, CA;

Chris Wysocki, Toronto, CA;

Assignee:

Altera Corporation, San Jose, CA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 19/003 (2006.01); G05F 1/46 (2006.01); H03K 19/0175 (2006.01); H03K 19/00 (2006.01);
U.S. Cl.
CPC ...
G05F 1/46 (2013.01); H03K 19/0175 (2013.01); H03K 19/0016 (2013.01);
Abstract

Programmable integrated circuits with configurable logic circuitry and routing resources are provided. Portions of the routing resources on a programmable integrated circuit may be used in implementing a desired user-specified custom logic function, whereas other portions of the routing resources on the programmable integrated circuit may be unused. The unused routing resources may include adjacent pairs of routing paths. These paths may be coupled to control circuitry configured to drive the routing paths to desired voltage levels to provide an optimal amount of decoupling capacitance. In one suitable arrangement, two adjacent routing paths may both be driven to a positive power supply voltage level. In another suitable arrangement, the two adjacent routing paths may be driven to the positive power supply voltage level and a ground power supply voltage level, respectively.


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