The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 03, 2016

Filed:

Jan. 26, 2015
Applicant:

Sumitomo Electric Industries, Ltd., Osaka-shi, Osaka, JP;

Inventors:

Takamitsu Kitamura, Fujisawa, JP;

Hideki Yagi, Machida, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/302 (2006.01); G02F 1/225 (2006.01); G06F 17/50 (2006.01); H01L 21/66 (2006.01); H01L 21/311 (2006.01); H01L 33/44 (2010.01); G02F 1/025 (2006.01); G02B 6/136 (2006.01); G02B 6/12 (2006.01); G02F 1/21 (2006.01);
U.S. Cl.
CPC ...
G02F 1/2257 (2013.01); G02B 6/136 (2013.01); G02F 1/025 (2013.01); G06F 17/5068 (2013.01); H01L 21/31116 (2013.01); H01L 22/12 (2013.01); H01L 22/20 (2013.01); H01L 33/44 (2013.01); G02B 2006/121 (2013.01); G02B 2006/12173 (2013.01); G02F 2001/212 (2013.01);
Abstract

A method for producing optical semiconductor devices includes: forming a stacked semiconductor layer on a device substrate to provide an epitaxial substrate having a size corresponding to a section arrangement; forming, on the epitaxial substrate, a mask having a pattern for a semiconductor mesa and for a trench of at least one optical semiconductor device, a width of the trench in the pattern being determined according to a trench width map in which trench width is based upon an in-plane distribution of the thickness of a resin layer of the at least one device, and upon a correlation between the thickness of the resin layer and the trench width; forming a trench structure including the semiconductor mesa and the trench by etching the stacked semiconductor layer using the mask; forming a resin layer on the trench structure; and forming an opening on the semiconductor mesa by etching the resin layer.


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