The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 26, 2016

Filed:

Apr. 08, 2015
Applicant:

Fujitsu Limited, Kawasaki-shi, Kanagawa, JP;

Inventors:

Mamoru Kurashina, Atsugi, JP;

Daisuke Mizutani, Sagamihara, JP;

Assignee:

FUJITSU LIMITED, Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/485 (2006.01); H05K 1/02 (2006.01); H01L 23/00 (2006.01); H01L 21/768 (2006.01); H01L 23/498 (2006.01); H01L 21/48 (2006.01); H05K 1/03 (2006.01); H05K 1/11 (2006.01);
U.S. Cl.
CPC ...
H05K 1/0271 (2013.01); H01L 21/4853 (2013.01); H01L 21/76877 (2013.01); H01L 23/49816 (2013.01); H01L 23/49822 (2013.01); H01L 23/49827 (2013.01); H01L 23/49833 (2013.01); H01L 23/49894 (2013.01); H01L 24/81 (2013.01); H05K 1/0298 (2013.01); H05K 1/0326 (2013.01); H05K 1/0346 (2013.01); H05K 1/115 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/08235 (2013.01); H01L 2224/131 (2013.01); H01L 2224/16235 (2013.01); H01L 2224/8121 (2013.01); H01L 2224/81191 (2013.01); H01L 2224/81815 (2013.01); H01L 2924/1306 (2013.01); H01L 2924/351 (2013.01); H05K 2201/0154 (2013.01); H05K 2201/09136 (2013.01); H05K 2201/10734 (2013.01);
Abstract

A semiconductor device manufacturing method includes: a first-process for placing, on a first-substrate on which traces and first-electrodes are formed, each of the first-electrodes being connected to one of traces, a second-substrate in which through-holes corresponding to the first-electrodes and relay-members are disposed, each of the relay-members being formed of solder, penetrating through one of the through-holes, and projecting from both ends of the one of the through-holes, so that the first-electrodes are aligned with the through-holes in a plan view; a second-process for melting the relay-members so that the relay-members are connected to the first-electrodes, after the first-process; and a third-process for placing a semiconductor substrate on which a second-electrodes corresponding to the first-electrodes are formed on a side opposite to the first-substrate across the second-substrate, after the second-process, to connect the first-electrodes and the second-electrodes to each other via the relay-members.


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