The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 26, 2016

Filed:

Oct. 18, 2012
Applicant:

Samsung Electronics Co. Ltd., Suwon-si, Gyeonggi-do, KR;

Inventors:

Younghee Ha, Yongin-si, KR;

Hyojae Cho, Yongin-si, KR;

Seyoung Jang, Seongnam-si, KR;

Seunghwan Cho, Yongin-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/00 (2006.01); G06F 1/26 (2006.01); G06F 1/32 (2006.01); H04W 52/02 (2009.01);
U.S. Cl.
CPC ...
H04W 52/029 (2013.01); H04W 52/027 (2013.01); H04W 52/0251 (2013.01); Y02B 60/50 (2013.01);
Abstract

A power saving apparatus and a method for a mobile terminal are provided. The method includes measuring a system load for a preset time during an application execution in a power saving mode, setting, when the measured system load exceeds a reference load level, a limit clock frequency as a maximum clock frequency for the power saving mode, measuring, in the power saving mode, the system load due to the application execution, performing, when the measured system load exceeds the reference load level, the application execution at the limit clock frequency, and performing, when the measured system load does not exceed the reference load level, the application execution at a system clock frequency corresponding to the measured system load, where performing the application execution at the limit clock frequency reduces a battery power consumption.


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