The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 26, 2016
Filed:
Aug. 22, 2013
Applicant:
Kabushiki Kaisha Toshiba, Minato-ku, JP;
Inventors:
Toshiyuki Umeda, Inagi, JP;
Shoji Otaka, Yokohama, JP;
Assignee:
KABUSHIKI KAISHA TOSHIBA, Minato-ku, JP;
Primary Examiner:
Int. Cl.
CPC ...
H03M 5/02 (2006.01); H04B 1/18 (2006.01); H02M 1/088 (2006.01); H02J 5/00 (2016.01); H03K 17/30 (2006.01);
U.S. Cl.
CPC ...
H04B 1/18 (2013.01); H02J 5/005 (2013.01); H02M 1/088 (2013.01); H03K 17/302 (2013.01); H03K 2017/307 (2013.01);
Abstract
A rectification circuit includes a first field-effect transistor and a bias voltage generation circuit. The field-effect transistor includes a first gate terminal, a first source terminal, a first source region having a first p-type diffusion layer and connected to the first source terminal, a first drain terminal, and a first drain region having a first n-type diffusion layer and connected to the first drain terminal. The bias voltage generation circuit is configured to apply a DC voltage between the first gate terminal and the first drain terminal.