The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 26, 2016
Filed:
Feb. 21, 2014
Applicant:
Pmc-sierra Us, Inc., Sunnyvale, CA (US);
Inventors:
Peter Graumann, Calgary, CA;
Sean Gibb, Calgary, CA;
Assignee:
Microsemi Storage Solutions (U.S.), Inc., Aliso Viejo, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03M 13/00 (2006.01); H03M 13/11 (2006.01); G11B 20/18 (2006.01); H03M 13/09 (2006.01); H04L 1/00 (2006.01); H03M 13/27 (2006.01);
U.S. Cl.
CPC ...
H03M 13/11 (2013.01); H03M 13/1111 (2013.01); H04L 1/0041 (2013.01); H04L 1/0057 (2013.01); G11B 20/1833 (2013.01); H03M 13/09 (2013.01); H03M 13/27 (2013.01); H04L 1/0061 (2013.01);
Abstract
A Forward Error Correction (FEC) decoder is provided, for example including a Layered Low Density Parity Check (LDPC) component. In an implementation, power consumption of the LDPC decoder is minimized with minimal to no impact on the error correction performance. This is achieved, in an implementation, by partially or fully eliminating redundant operations in the iterative process.