The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 26, 2016

Filed:

Mar. 10, 2014
Applicant:

Pmc-sierra, Inc., Sunnyvale, CA (US);

Inventors:

Guillaume Fortin, Verdun, CA;

Charles Roy, St-Jerome, CA;

Mathieu Gagnon, Verdun, CA;

Assignee:

Microsemi Storage Solutions, Inc., Aliso Viejo, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 19/094 (2006.01); H03K 17/14 (2006.01); H03K 19/003 (2006.01);
U.S. Cl.
CPC ...
H03K 17/145 (2013.01); H03K 19/00384 (2013.01);
Abstract

Apparatus and methods advantageously maintain transistors of open-drain differential pairs biased in the saturation region when 'active,' rather in than the triode or linear region. The biasing techniques are effective over a broad range of process, voltage, and temperature (PVT) variations. By controlling a high voltage level used to drive the gate of a transistor of the differential pair, the biasing of the transistor in the saturation region is maintained. In one embodiment, the low voltage level used to cut off the transistor of the differential pair is also controlled. These techniques advantageously permit differential drivers to exhibit relatively large output swings, relatively high edge rates, relatively high return loss, and relatively good efficiency.


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