The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 26, 2016
Filed:
Dec. 19, 2013
University of Electronic Science and Technology of China, Sichuan, CN;
Junhong Li, Sichuan, CN;
Ping Li, Sichuan, CN;
UNIVERSITY OF ELECTRONIC SCIENCE AND TECHNOLOGY OF CHINA, Chengdu, CN;
Abstract
Provided is a lateral power device having low specific ON-resistance and using a high-dielectric constant socket structure and a manufacturing method therefor, which relate to semiconductor power devices. A source electrode () of the device is of a first conduction type, and a channel region (), a silicon substrate () and an ohmic contact heavily-doped region are of a second conduction type; at least two isolation regions are arranged in an embedded manner in a drift region (); between the isolation regions are the drift region () and the channel region (); each isolation region extends from the source electrode () to a drain electrode (); high-dielectric constant material strips () and first insulation dielectric layers () form boundaries of the bottoms and sidewalls of the isolation regions; the isolation regions are filled with a first filling material (), a second insulation dielectric layer () is arranged on the upper surface of the drift region () and the upper surfaces of the isolation regions, and a gate electrode () directly contacts the first filling material () via holes on the second insulation dielectric layer (); and a source electrode lead-out wire () and a drain electrode lead-out wire () directly contact the source electrode () and the drain electrode () respectively via the holes on the second insulation dielectric layer (). The area of a power device can be greatly reduced on the premise of not reducing the withstand voltage and not increasing the specific ON-resistance.