The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 26, 2016
Filed:
Mar. 27, 2015
Applicant:
Imec Vzw, Leuven, BE;
Inventors:
Assignee:
IMEC VZW, Leuven, BE;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/41 (2006.01); B82Y 10/00 (2011.01); B82Y 40/00 (2011.01); H01L 29/66 (2006.01); H01L 29/775 (2006.01); H01L 29/06 (2006.01); H01L 29/10 (2006.01); H01L 29/20 (2006.01); H01L 29/04 (2006.01); H01L 29/423 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 29/413 (2013.01); B82Y 10/00 (2013.01); B82Y 40/00 (2013.01); H01L 29/04 (2013.01); H01L 29/0649 (2013.01); H01L 29/0673 (2013.01); H01L 29/1079 (2013.01); H01L 29/20 (2013.01); H01L 29/42392 (2013.01); H01L 29/6681 (2013.01); H01L 29/66469 (2013.01); H01L 29/775 (2013.01); H01L 29/7853 (2013.01);
Abstract
The disclosed technology generally relates to semiconductor devices and more particularly to a gate-all-around semiconductor device, and methods of fabricating the same. In one aspect, the method comprises providing on a semiconductor substrate between STI regions at least one suspended nanostructure anchored by a source region and a drain region. The suspended nanostructure is formed of a crystalline semiconductor material that is different from a crystalline semiconductor material of the semiconductor substrate. A gate stack surrounds the at least one suspended nanostructure.