The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 26, 2016

Filed:

Sep. 17, 2014
Applicant:

Mitsubishi Electric Corporation, Tokyo, JP;

Inventor:

Yasunari Hino, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/40 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 24/83 (2013.01); H01L 24/29 (2013.01); H01L 24/32 (2013.01); H01L 24/45 (2013.01); H01L 24/48 (2013.01); H01L 24/73 (2013.01); H01L 24/85 (2013.01); H01L 2224/04042 (2013.01); H01L 2224/29007 (2013.01); H01L 2224/29014 (2013.01); H01L 2224/29339 (2013.01); H01L 2224/29347 (2013.01); H01L 2224/29364 (2013.01); H01L 2224/32014 (2013.01); H01L 2224/32055 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/32245 (2013.01); H01L 2224/45015 (2013.01); H01L 2224/45124 (2013.01); H01L 2224/48137 (2013.01); H01L 2224/48472 (2013.01); H01L 2224/73265 (2013.01); H01L 2224/8384 (2013.01); H01L 2224/83203 (2013.01); H01L 2224/92247 (2013.01); H01L 2924/13055 (2013.01); H01L 2924/13091 (2013.01); H01L 2924/15787 (2013.01); H01L 2924/181 (2013.01); H01L 2924/351 (2013.01);
Abstract

A manufacturing method of a semiconductor device according to the present invention includes the steps of (a) preparing an insulating or conductive substrate; (b) arranging a bonding material having sinterability in at least one bonding region of a principal surface of the substrate (i.e., insulating substrate); and (c) sintering the bonding material while a bonding surface to be subjected to bonding of at least one semiconductor element is brought into pressurized contact with the bonding material, and bonding the substrate (i.e., insulating substrate) and the semiconductor element together through the bonding material. The bonding region in the step (b) is inwardly positioned from the bonding surface (i.e., region) of the semiconductor element in plan view, and the bonding material is not protruded outwardly from the bonding surface of the semiconductor element in plan view even after the step (c).


Find Patent Forward Citations

Loading…