The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 26, 2016

Filed:

Mar. 30, 2015
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Inventors:

Doo-Jin Kim, Cheonan-si, KR;

Young-Sik Kim, Cheonan-si, KR;

Tea-Seog Um, Asan-si, KR;

Yong-Dae Ha, Asan-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/544 (2006.01); H01L 23/52 (2006.01); H01L 25/07 (2006.01); H01L 25/00 (2006.01); H01L 21/67 (2006.01); H01L 21/683 (2006.01);
U.S. Cl.
CPC ...
H01L 23/544 (2013.01); H01L 21/67144 (2013.01); H01L 25/074 (2013.01); H01L 25/50 (2013.01); H01L 21/6836 (2013.01); H01L 2221/68354 (2013.01); H01L 2221/68381 (2013.01); H01L 2223/54426 (2013.01); H01L 2223/54486 (2013.01); H01L 2224/05553 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48145 (2013.01); H01L 2224/48147 (2013.01); H01L 2224/73265 (2013.01); H01L 2225/06562 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/181 (2013.01);
Abstract

An aligning guide, a semiconductor package comprising an aligning guide, and a method of manufacturing a semiconductor package comprising an aligning guide are provided. The semiconductor package may comprise a circuit board and an aligning guide mounted on the circuit board. The aligning guide may have a plurality of stepped portions. A plurality of semiconductor chips may be stacked on the circuit board and engage with the stepped portions of the aligning guide. According to the disclosed semiconductor package, a large number of semiconductor chips may be stacked with high accuracy and sufficient margin. Therefore, the rate of failure and defects in the chip stacking process may be reduced and the reliability and stability of the semiconductor package may be enhanced.


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