The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 26, 2016

Filed:

Feb. 25, 2015
Applicants:

Sang-won Park, Seoul, KR;

Dongku Kang, Seongnam-si, KR;

Jung-yun Yun, Seoul, KR;

Jinman Han, Seongnam-si, KR;

Chiweon Yoon, Seoul, KR;

Inventors:

Sang-Won Park, Seoul, KR;

Dongku Kang, Seongnam-si, KR;

Jung-Yun Yun, Seoul, KR;

Jinman Han, Seongnam-si, KR;

ChiWeon Yoon, Seoul, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/16 (2006.01); G11C 16/14 (2006.01); G11C 16/04 (2006.01); G11C 16/34 (2006.01);
U.S. Cl.
CPC ...
G11C 16/14 (2013.01); G11C 16/0483 (2013.01); G11C 16/16 (2013.01); G11C 16/3445 (2013.01);
Abstract

The inventive concept relates to a nonvolatile memory device and methods for operating the same. The nonvolatile memory device comprises a plurality of strings arranged in rows and columns on a substrate, each string including at least one ground select transistor, a plurality of memory cells and at least one string select transistor sequentially stacked on the substrate. The method comprises erasing first memory cells corresponding to an erasure failed row and inhibiting erasure of second memory cells corresponding to an erasure passed row, and performing an erasure verification by a unit of each row with respect to the first memory cells.


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