The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 26, 2016
Filed:
Mar. 22, 2012
Applicants:
Tae Sun Hwang, Gyeonggi-do, KR;
IN Sun Park, Gyeonggi-do, KR;
Inventors:
Tae Sun Hwang, Gyeonggi-do, KR;
In Sun Park, Gyeonggi-do, KR;
Assignee:
INDUSTRIAL BANK OF KOREA, Seoul, KR;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); G11C 16/04 (2006.01); G11C 16/08 (2006.01); G11C 16/24 (2006.01); G11C 16/26 (2006.01); G11C 16/32 (2006.01); G11C 7/22 (2006.01); G11C 8/16 (2006.01); G06F 12/00 (2006.01);
U.S. Cl.
CPC ...
G06F 3/064 (2013.01); G06F 3/0619 (2013.01); G06F 3/0688 (2013.01); G11C 7/22 (2013.01); G11C 8/16 (2013.01); G11C 16/0483 (2013.01); G11C 16/08 (2013.01); G11C 16/24 (2013.01); G11C 16/26 (2013.01); G11C 16/32 (2013.01); G11C 2216/30 (2013.01);
Abstract
Disclosed is a method of reading data from a memory including a NAND cell array for performing communications via a serial peripheral interface (SPI) bus. The method includes sequentially receiving inputs of a block address, a word-line address, and a bit-line address of the NAND cell array; and starting to output data written in the NAND cell array immediately after the bit-line address is completely input. In this case, the sequential receiving of the inputs is performed via one input terminal.