The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 19, 2016

Filed:

Feb. 19, 2014
Applicant:

Microchip Technology Incorporated, Chandler, AZ (US);

Inventors:

Paul Fest, Chandler, AZ (US);

James Walls, Mesa, AZ (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 45/00 (2006.01); H01L 27/24 (2006.01);
U.S. Cl.
CPC ...
H01L 45/1273 (2013.01); H01L 27/2463 (2013.01); H01L 45/08 (2013.01); H01L 45/122 (2013.01); H01L 45/1608 (2013.01); H01L 45/1675 (2013.01); H01L 45/1683 (2013.01);
Abstract

A method of forming a resistive memory cell, e.g., a CBRAM or ReRAM, may include forming a bottom electrode layer, oxidizing an exposed region of the bottom electrode layer to form an oxide region, removing a region of the bottom electrode layer proximate the oxide region, thereby forming a bottom electrode having a pointed tip region adjacent the oxide region, and forming an electrolyte region and top electrode over at least a portion of the bottom electrode and oxide region, such that the electrolyte region is arranged between the pointed tip region of the bottom electrode and the top electrode, and provides a path for conductive filament or vacancy chain formation from the pointed tip region of the bottom electrode to the top electrode when a voltage bias is applied to the memory cell. A memory cell and memory cell array formed by such method are also disclosed.


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