The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 19, 2016

Filed:

Jun. 23, 2015
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Lyndon R. Logan, Poughkeepsie, NY (US);

Edward J. Nowak, Essex Junction, VT (US);

Robert R. Robison, Colchester, VT (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 31/00 (2006.01); H01L 29/868 (2006.01); H01L 27/08 (2006.01); H01L 29/16 (2006.01); H01L 27/146 (2006.01); H01L 31/105 (2006.01); H01L 31/0368 (2006.01); H01L 29/66 (2006.01); H01L 21/02 (2006.01);
U.S. Cl.
CPC ...
H01L 29/868 (2013.01); H01L 21/02532 (2013.01); H01L 21/02595 (2013.01); H01L 21/02672 (2013.01); H01L 27/0814 (2013.01); H01L 27/14643 (2013.01); H01L 29/16 (2013.01); H01L 29/6609 (2013.01); H01L 29/66545 (2013.01); H01L 31/03685 (2013.01); H01L 31/105 (2013.01);
Abstract

Structures and methods of manufacturing a fin-type PIN diode array include forming a plurality of first charge-type doped silicon fins disposed in parallel on a planar substrate in a first direction, forming undoped epitaxial growths of silicon at intervals along a length of each silicon fin, where each epitaxial growth includes a depleted intrinsic region, and forming a plurality of second charge-type doped polysilicon fins disposed in parallel and disposed perpendicularly to the first direction. The polysilicon fins are formed to contact, at intervals along a length of each polysilicon fin, an uppermost surface of one of the undoped epitaxial growths of silicon, to form a PIN diode at each intersection of each of the first charge-type doped silicon fins and the second charge-type doped polysilicon fins.


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