The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 19, 2016
Filed:
Apr. 13, 2015
Applicant:
Apple Inc., Cupertino, CA (US);
Inventors:
Assignee:
Apple Inc., Cupertino, CA (US);
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/02 (2006.01); H01L 27/088 (2006.01); H01L 29/06 (2006.01); H01L 29/744 (2006.01); H01L 29/10 (2006.01); H01L 27/06 (2006.01); H01L 29/74 (2006.01); H01L 21/00 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0259 (2013.01); H01L 27/0635 (2013.01); H01L 27/0886 (2013.01); H01L 29/0649 (2013.01); H01L 29/1095 (2013.01); H01L 29/744 (2013.01); H01L 29/7436 (2013.01);
Abstract
In an embodiment, an ESD protection circuit may include an STI-bound SCR and a gated SCR that may be electrically in parallel with the STI-bound SCR. The gated SCR may be perpendicular to the STI-bound SCR in a plane of the semiconductor substrate. In an embodiment, the gated SCR may trigger more quickly and turn on more quickly than the STI-bound SCR. The STI-bound SCR may form the main current path for an ESD event. A low capacitive load with rapid response to ESD events may thus be formed. In an embodiment, the anode of the two SCRs may be shared.