The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 19, 2016
Filed:
May. 21, 2013
Applicant:
David H. Eppes, Driftwood, TX (US);
Inventor:
David H. Eppes, Driftwood, TX (US);
Assignee:
Advanced Micro Devices, Inc., Sunnyvale, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/498 (2006.01); H01L 23/48 (2006.01); H01L 21/50 (2006.01); H01L 23/02 (2006.01); H01L 23/00 (2006.01); H01L 25/00 (2006.01); H01L 21/66 (2006.01); H01L 25/065 (2006.01);
U.S. Cl.
CPC ...
H01L 24/81 (2013.01); H01L 22/20 (2013.01); H01L 24/16 (2013.01); H01L 24/17 (2013.01); H01L 24/98 (2013.01); H01L 25/50 (2013.01); H01L 22/14 (2013.01); H01L 24/13 (2013.01); H01L 25/0657 (2013.01); H01L 2224/131 (2013.01); H01L 2224/13082 (2013.01); H01L 2224/13109 (2013.01); H01L 2224/13111 (2013.01); H01L 2224/13116 (2013.01); H01L 2224/13139 (2013.01); H01L 2224/13144 (2013.01); H01L 2224/13147 (2013.01); H01L 2224/13164 (2013.01); H01L 2224/13169 (2013.01); H01L 2224/1601 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/17181 (2013.01); H01L 2224/17505 (2013.01); H01L 2224/81815 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06565 (2013.01); H01L 2924/01322 (2013.01); H01L 2924/12042 (2013.01); H01L 2924/15311 (2013.01);
Abstract
Various methods of mounting semiconductor chips on a substrate are disclosed. In one aspect, a method of manufacturing is provided that includes coupling a first plurality of solder interconnect structures to a first semiconductor chip. The first solder interconnect structures have a first melting point. The first semiconductor chip may be tested. If the first semiconductor chip passes the testing, then a second semiconductor chip is coupled to the first semiconductor chip using a second plurality of solder interconnect structures that have a second melting point lower than the first melting point.