The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 19, 2016

Filed:

Oct. 31, 2013
Applicants:

Tim V. Pham, Austin, TX (US);

Michael B. Mcshane, Austin, TX (US);

Perry H. Pelley, Austin, TX (US);

Tab A. Stephens, Austin, TX (US);

Inventors:

Tim V. Pham, Austin, TX (US);

Michael B. McShane, Austin, TX (US);

Perry H. Pelley, Austin, TX (US);

Tab A. Stephens, Austin, TX (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 23/52 (2006.01); H01L 23/02 (2006.01); H01L 23/00 (2006.01); H01L 25/065 (2006.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
H01L 24/02 (2013.01); H01L 24/48 (2013.01); H01L 24/80 (2013.01); H01L 24/92 (2013.01); H01L 25/0657 (2013.01); H01L 24/29 (2013.01); H01L 24/32 (2013.01); H01L 24/45 (2013.01); H01L 24/83 (2013.01); H01L 24/85 (2013.01); H01L 29/0657 (2013.01); H01L 2224/04 (2013.01); H01L 2224/04042 (2013.01); H01L 2224/2919 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/45124 (2013.01); H01L 2224/45144 (2013.01); H01L 2224/45147 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48145 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/48465 (2013.01); H01L 2224/73265 (2013.01); H01L 2224/80001 (2013.01); H01L 2224/92165 (2013.01); H01L 2225/0651 (2013.01); H01L 2225/06506 (2013.01); H01L 2924/10156 (2013.01); H01L 2924/10158 (2013.01); H01L 2924/12042 (2013.01); H01L 2924/15311 (2013.01);
Abstract

A first semiconductor device die is provided having a bottom edge incorporating a notch structure that allows sufficient height and width clearance for a wire bond connected to a bond pad on an active surface of a second semiconductor device die upon which the first semiconductor device die is stacked. Use of such notch structures reduces a height of a stack incorporating the first and second semiconductor device die, thereby also reducing a thickness of a semiconductor device package incorporating the stack.


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