The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 19, 2016
Filed:
May. 18, 2005
Applicant:
Heimo Scheucher, Langegg, AT;
Inventor:
Heimo Scheucher, Langegg, AT;
Assignee:
NXP B.V., Eindhoven, NL;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 23/498 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49855 (2013.01); H01L 23/49833 (2013.01); H01L 24/05 (2013.01); H01L 24/11 (2013.01); H01L 24/12 (2013.01); H01L 24/13 (2013.01); H01L 24/10 (2013.01); H01L 24/49 (2013.01); H01L 2224/04042 (2013.01); H01L 2224/05553 (2013.01); H01L 2224/05554 (2013.01); H01L 2224/05599 (2013.01); H01L 2224/48137 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/49171 (2013.01); H01L 2224/85399 (2013.01); H01L 2924/00014 (2013.01); H01L 2924/01005 (2013.01); H01L 2924/01006 (2013.01); H01L 2924/01013 (2013.01); H01L 2924/01014 (2013.01); H01L 2924/01022 (2013.01); H01L 2924/01033 (2013.01); H01L 2924/01074 (2013.01); H01L 2924/01082 (2013.01); H01L 2924/05042 (2013.01); H01L 2924/14 (2013.01);
Abstract
A chip () has a substrate (), an integrated circuit () provided on the substrate (), a plurality of conductor zones (ME, ME, ME, ME, ME) and a passivating layer () provided to protect the conductor zones and the integrated circuit, through-holes () being provided in the passivating layer () through which chip contacts () are accessible, wherein additional chip contacts () and connecting conductors () are provided on the passivating layer () and wherein each additional chip contact has an electrically conductive connection to a chip contact via a connecting conductor.