The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 19, 2016

Filed:

Dec. 18, 2012
Applicant:

SK Hynix Inc., Icheon-si, Gyeonggi-do, KR;

Inventor:

Moon Soo Kim, Seoul, KR;

Assignee:

SK HYNIX INC., Icheon-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/488 (2006.01); H01L 23/00 (2006.01); H01L 25/065 (2006.01); G11C 5/06 (2006.01);
U.S. Cl.
CPC ...
H01L 23/488 (2013.01); G11C 5/063 (2013.01); H01L 24/06 (2013.01); H01L 24/48 (2013.01); H01L 24/49 (2013.01); H01L 25/0652 (2013.01); H01L 25/0657 (2013.01); H01L 2224/05553 (2013.01); H01L 2224/0612 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48111 (2013.01); H01L 2224/48145 (2013.01); H01L 2224/48147 (2013.01); H01L 2224/49175 (2013.01); H01L 2225/0651 (2013.01); H01L 2225/06506 (2013.01); H01L 2225/06572 (2013.01); H01L 2924/00014 (2013.01); H01L 2924/13091 (2013.01); H01L 2924/15192 (2013.01);
Abstract

A stack package including a first semiconductor chip and second semiconductor chip, the first semiconductor chip including first data I/O pads for transmitting data I/O signals, a first flag pad for receiving a flag signal, and a first buffer for controlling a switching operation between the first data I/O pads and an internal circuit of the first semiconductor chip. The second semiconductor chip includes second data I/O pads for transmitting the data I/O signals, a second flag pad for receiving the flag signal, and a second buffer for controlling a switching operation between the second data I/O pads and an internal circuit of the second semiconductor chip. The first data I/O pads are electrically connected to respective ones of the second data I/O pads through first wires, and the first flag pad is electrically connected to the second flag pad through a second wire. Related methods are also provided.


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