The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 19, 2016

Filed:

Feb. 02, 2010
Applicants:

Takayuki Kawahara, Higashiyamato, JP;

Riichiro Takemura, Tokyo, JP;

Kazuo Ono, Hachioji, JP;

Nobuaki Kohinata, Los Gatos, CA (US);

Inventors:

Takayuki Kawahara, Higashiyamato, JP;

Riichiro Takemura, Tokyo, JP;

Kazuo Ono, Hachioji, JP;

Nobuaki Kohinata, Los Gatos, CA (US);

Assignee:

Hitachi, Ltd., Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01); G11C 11/15 (2006.01); G11C 11/16 (2006.01);
U.S. Cl.
CPC ...
G11C 11/15 (2013.01); G11C 11/16 (2013.01);
Abstract

Since a nonvolatile RAM allows random reading and writing operations, an erasing mode is unnecessary. From the system side, however, it is desirable to have the erasing mode because of its nonvolatile characteristic. Moreover, the erasing operation is desirably carried out at high speed with low power consumption. Therefore, memory cell arrays COA and DTA containing a plurality of memory cells MC each having a magnetoresistive element are provided, a series of data is written to the memory cell arrays COA and DTA, and at the time of erasing, an erasing operation is carried out by writing predetermined data only to the memory cell array COA.


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