The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 19, 2016
Filed:
Feb. 26, 2013
Applicant:
Ps4 Luxco S.a.r.l., Luxembourg, LU;
Inventor:
Hiroaki Iwaki, Tokyo, JP;
Assignee:
PS4 Lucxo S.a.r.l., Luxembourg, LU;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 5/06 (2006.01); G11C 11/4097 (2006.01); H01L 27/02 (2006.01); H01L 27/108 (2006.01); H01L 23/522 (2006.01);
U.S. Cl.
CPC ...
G11C 5/063 (2013.01); G11C 5/06 (2013.01); G11C 11/4097 (2013.01); H01L 23/5222 (2013.01); H01L 27/0207 (2013.01); H01L 27/10811 (2013.01); H01L 27/10885 (2013.01); H01L 27/10876 (2013.01); H01L 2924/0002 (2013.01);
Abstract
Disclosed herein is a semiconductor device including a multi-level wiring structure that includes a lower-level wiring, an upper-level wiring and an interlayer insulating film between the lower-level and upper-level wirings. The device further includes a plurality of bit lines for a plurality of memory cells, and each of the bit lines includes a first portion that is formed as the lower-level wiring and a second portion that is electrically connected in series to the first portion and formed as the upper-level wiring.