The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 19, 2016

Filed:

Mar. 16, 2015
Applicant:

Atmel Corporation, San Jose, CA (US);

Inventors:

Guillaume Pean, Aix-en-Provence, FR;

Franck Lunadier, Trets, FR;

Alain Vergnes, Trets, FR;

Assignee:

Atmel Corporation, San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/00 (2006.01); G06F 13/364 (2006.01); G06F 13/28 (2006.01); G06F 13/40 (2006.01); H04L 9/06 (2006.01);
U.S. Cl.
CPC ...
G06F 13/364 (2013.01); G06F 13/00 (2013.01); G06F 13/28 (2013.01); G06F 13/4022 (2013.01); H04L 9/0631 (2013.01);
Abstract

A system includes one or more master modules configured to execute instructions embedded in non-transitory machine-readable media and controllable by a processor. The system also includes one or more peripheral modules that are configured to execute instructions embedded in non-transitory machine-readable media and controllable by the processor. The system also includes a system bus with instructions embedded in a non-transitory machine-readable medium and configured to allow data transfer between the processor and the one or more peripheral modules. A data processing module of the one or more peripheral modules includes a master interface and a slave interface. Both master and slave interfaces are coupled to the system bus.


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