The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 19, 2016

Filed:

Nov. 18, 2013
Applicant:

Amazon Technologies, Inc., Reno, NV (US);

Inventors:

Kent David Forschmiedt, Shoreline, WA (US);

Nicholas Patrick Wilt, Mercer Island, WA (US);

Matthew David Klein, Seattle, WA (US);

Assignee:

Amazon Technologies, Inc., Reno, NV (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 12/14 (2006.01); G06F 12/10 (2006.01); G06F 9/455 (2006.01);
U.S. Cl.
CPC ...
G06F 12/1458 (2013.01); G06F 9/45558 (2013.01); G06F 12/1009 (2013.01); G06F 12/145 (2013.01); G06F 12/1483 (2013.01); G06F 12/1491 (2013.01);
Abstract

A virtual machine environment in which a hypervisor provides direct memory mapped access by a virtual guest to a physical memory device. The hypervisor prevents reading from, writing to, or both, any individual register or registers while allowing unrestricted access to other registers, and without raising any abnormal condition in the guest's execution environment. For example, in one embodiment, the hypervisor can apply memory access protection to a memory page containing a restricted register so that a fault condition can be raised. When an instruction is executed, the hypervisor can intercept the fault condition and emulate the faulting guest instruction. When the emulation accesses the restricted address, the hypervisor can selectively decide whether or not to perform the access.


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