The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 19, 2016
Filed:
Jan. 08, 2015
Applicant:
Kabushiki Kaisha Toshiba, Minato-ku, JP;
Inventors:
Assignee:
KABUSHIKI KAISHA TOSHIBA, Minato-ku, JP;
Primary Examiner:
Int. Cl.
CPC ...
G06F 21/00 (2013.01); G06F 12/14 (2006.01); G06F 12/02 (2006.01); G06F 11/14 (2006.01); G06F 11/10 (2006.01); G06F 21/79 (2013.01); G09C 1/00 (2006.01); H04L 9/06 (2006.01); G06F 21/60 (2013.01); G06F 11/30 (2006.01);
U.S. Cl.
CPC ...
G06F 12/1408 (2013.01); G06F 11/1068 (2013.01); G06F 11/1412 (2013.01); G06F 12/02 (2013.01); G06F 21/602 (2013.01); G06F 21/79 (2013.01); G09C 1/00 (2013.01); H04L 9/0631 (2013.01); G06F 12/0246 (2013.01); G06F 2212/1044 (2013.01); G06F 2212/1052 (2013.01); G06F 2212/7203 (2013.01); H04L 2209/12 (2013.01); H04L 2209/46 (2013.01);
Abstract
According to one embodiment, a nonvolatile semiconductor storage device includes an encrypting circuit for operating in a predetermined encrypting system, a memory cell array preliminarily storing complementary data to be used in the operation, and a page buffer having a first region for storing the data being read out from the memory cell array, and a second region used when executing the operation.